In STFC’s science laboratories physicists want to watch very fast processes such as proteins folding in biological samples, how cracks propagate in metals or ceramics and bubbles form in liquids as well as many other applications. This makes high-speed data driving circuits critical design blocks that we must have ready in our libraries to use in our imaging chips for tomorrow’s systems.
Many of the imaging systems we have planned will create over half a gigabit of digital data per frame, and these systems will then have to be capable of transmitting that data to storage at millions of frames per second. Scaling our existing methods of transmission at low speeds that happens via multiple parallel data lines from each chip is becoming unmanageable due to the numbers of connections involved, so we know a different approach is required.
Within Work Package 1 of the Centre for Instrumentation's Microelectronics Managed Programme, an ultra-fast circuit has been developed that transmits data as an encoded serial data stream at a rate of 10Gb/s on a single output wire pair. This circuit builds on a commercial standard developed for high speed networks (the Aurora 64-66bit protocol) and has been manufactured in a 65nm silicon chip process that we expect to use for future projects.
The prototype works very well with no bit-errors detected during tests that ran for more than 60 hours at a rate of 10.312Gb/s, proving that our design works to specification. Development activity such as this enables us to build a strong libraries of tested components that can then be reliably deployed in tomorrow’s systems.
A photograph of the test chip (2x2mm) and below it the eye diagram measured for the manufactured circuit.
Last updated: 16 November 2018